rus
Issue #1/2025
A.V. Strogonov, A. Vinokurov, A.I. Strogonov, A. Arsentiev
DEVELOPMENT OF A MULTI-CYCLE RISC-V MICROPROCESSOR CORE FOR IMPLEMENTATION ON THE CYCLONE V FPGA BASIS
DEVELOPMENT OF A MULTI-CYCLE RISC-V MICROPROCESSOR CORE FOR IMPLEMENTATION ON THE CYCLONE V FPGA BASIS
DOI: 10.22184/1992-4178.2025.242.1.96.100
The article discusses the development of a multi-cycle RISC-V microprocessor core with a control machine created using State Machine Editor in the Altera Quartus II CAD system for subsequent implementation on the Cyclone V series FPGA basis.
Tags: altera quartus ii cad cyclone v fpga risc-v architecture state machine editor архитектура risc-v плис cyclone v редактор конечных автоматов сапр altera quartus ii
Subscribe to the journal Electronics: STB to read the full article.
The article discusses the development of a multi-cycle RISC-V microprocessor core with a control machine created using State Machine Editor in the Altera Quartus II CAD system for subsequent implementation on the Cyclone V series FPGA basis.
Tags: altera quartus ii cad cyclone v fpga risc-v architecture state machine editor архитектура risc-v плис cyclone v редактор конечных автоматов сапр altera quartus ii
Subscribe to the journal Electronics: STB to read the full article.
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