rus
Issue #9/2024
A.V. Strogonov, A. Vinokurov, A.I. Strogonov
EXAMPLE OF IMPLEMENTATION OF A SINGLE-CYCLE RISC-V PROCESSOR CORE USING ALTERA QUARTUS II CAD
EXAMPLE OF IMPLEMENTATION OF A SINGLE-CYCLE RISC-V PROCESSOR CORE USING ALTERA QUARTUS II CAD
DOI: 10.22184/1992-4178.2024.240.9.70.79
One of the areas of work in the field of creating projects based on the RISC-V architecture is the development of prototypes of processors on the FPGA platform. The article considers an example of the implementation of a single-cycle RISC-V processor core on the Cyclone V FPGA basis using the Altera Quartus II CAD system.
Tags: altera quartus ii cad fpga risc-v architecture rtl representation rtl-представление vhdl code vhdl-код архитектура risc-v плис сапр altera quartus ii
Subscribe to the journal Electronics: STB to read the full article.
One of the areas of work in the field of creating projects based on the RISC-V architecture is the development of prototypes of processors on the FPGA platform. The article considers an example of the implementation of a single-cycle RISC-V processor core on the Cyclone V FPGA basis using the Altera Quartus II CAD system.
Tags: altera quartus ii cad fpga risc-v architecture rtl representation rtl-представление vhdl code vhdl-код архитектура risc-v плис сапр altera quartus ii
Subscribe to the journal Electronics: STB to read the full article.
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