rus
Issue #1/2026
A. Strogonov
FEATURES OF THE IMPLEMENTATION OF A PIPELINED RISC-V PROCESSOR CORE ON THE FPGA BASIS
FEATURES OF THE IMPLEMENTATION OF A PIPELINED RISC-V PROCESSOR CORE ON THE FPGA BASIS
DOI: 10.22184/1992-4178.2026.253.1.122.127
The article discusses the design features of a 5-stage pipelined RISC-V processor core in Altera Quartus Prime Standard Edition CAD for subsequent implementation on the Cyclone V series FPGA basis.
Tags: code synthesis hardware description language modelsim altera pipeline processor risc-v architecture архитектура risc-v конвейерный процессор синтез кода язык описания аппаратуры
Subscribe to the journal Electronics: STB to read the full article.
The article discusses the design features of a 5-stage pipelined RISC-V processor core in Altera Quartus Prime Standard Edition CAD for subsequent implementation on the Cyclone V series FPGA basis.
Tags: code synthesis hardware description language modelsim altera pipeline processor risc-v architecture архитектура risc-v конвейерный процессор синтез кода язык описания аппаратуры
Subscribe to the journal Electronics: STB to read the full article.
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